README.md

Lab 16: CR–RC² Shaping Amplifier

In this lab, we implement a CR–RC² shaping amplifier in Sci‐Compiler. The CR (high‐pass) stage and RC² (two consecutive low‐pass filters) stage together create a classic pulse‐shaping network frequently used in nuclear pulse spectroscopy and other signal processing applications where pulses must be transformed into a well‐defined shape.

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1. Introduction to CR–RC² Shaping

Why Use a Shaping Amplifier?

In many detector readout systems (e.g., radiation detectors, photodiodes, or scintillation counters), the raw signals are often short pulses on top of a baseline. These signals can have:

• Noise in both low‐frequency (baseline drift) and high‐frequency (electronic noise) regimes.
• Varying pulse lengths that can complicate measurement of pulse amplitude or area.

A CR–RC² network shapes each pulse to:

1. Reduce Low‐Frequency Noise by filtering out slow variations in the baseline (the CR differentiator acts as a high‐pass filter).
2. Limit High‐Frequency Noise by smoothing the signal with the RC² low‐pass sections (two integrator stages).
3. Produce a More Uniform Pulse Shape that is easier to measure for amplitude (peak detection) or to integrate for charge measurement.

Theoretical Overview

1. CR (High‐Pass) Stage

   • Conceptually differentiates the input signal.
   • Removes slow drifts and offsets in the baseline (frequencies near DC).
   • The output appears as a short “spike” in response to a step or rapidly changing signal.

2. RC² (Double Low‐Pass) Stage

   • Two cascaded RC filters.
   • Each RC filter has a time constant (\tau = RC).
   • In the time domain, these integrators shape the short spikes from the CR stage into semi‐Gaussian or “rounded” pulses with controlled rise and fall times.

The result is a semi‐Gaussian‐like output that peaks at a well‐defined time after each pulse arrives. This shape helps reduce noise contributions and provides consistent pulse height measurement.

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2. Hardware/FPGA Implementation in Sci‐Compiler

Below is the simplified block diagram in Sci‐Compiler:

1. Analog In Pin – The raw 16‐bit ADC input.
2. Unsigned <-> Signed Converters – Convert the 16‐bit unsigned ADC to a signed format for filtering.
3. Butterworth (IIR‐I) Filter – Configured as a High Pass (CR) filter.
4. FX GAIN – A digital gain stage.
5. Butterworth (IIR‐II) Filter – Configured as a Low Pass (the RC² portion), repeated if needed.
6. Oscilloscope – Displays both the input and shaped outputs.

Note: In traditional analog electronics, you would have a resistor‐capacitor network for CR, followed by two RC integrators. In Sci‐Compiler, we approximate these with digital IIR filters: one high‐pass and two low‐pass sections.

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3. CR–RC² Filter Configuration

3.1 CR (High Pass)

• Cutoff Frequency: Set in the filter’s properties (e.g., 1 MHz or 50 kHz, etc.).
• This stage attenuates DC and low‐frequency components.
• In classical analog design, the time constant (\tau_d = R \times C) determines how quickly the output returns to zero after a pulse.

3.2 RC² (Low Pass)

• Two cascaded low‐pass filters, each with its own cutoff frequency (e.g., 100 kHz).
• Each integrator extends the pulse shape in time, limiting fast fluctuations (noise).
• The overall time constant (\tau_i) can be chosen to set how wide you want the shaped pulse to be.

3.3 Gain Stage

• An FX GAIN block applies a digital multiplication after the CR filter to scale the signal.
• Internally, OUT = (Gain × IN) / 256, allowing fine adjustments without saturating the FPGA’s internal signal width.

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4. Example Oscilloscope Traces

Input vs. Shaped Outputs

1. Channel 1 (Blue) – The raw ADC input, showing a series of exponential pulses with a 50 µs decay time.
2. Channel 2 (Green) – The CR (high‐pass) output, looks like a quick positive spike, returning to baseline.
3. Channel 3 (Cyan) – The final RC² output, a smoother pulse with a distinct peak and decay.

Zoomed‐In View

Here you see:

• Green spike from the CR differentiator.
• Cyan shape from the double RC² integration, providing a gently rising and falling pulse.

5. Why CR–RC² is Widely Used

• Noise Reduction: By eliminating low‐frequency drift and high‐frequency noise, the SNR (Signal‐to‐Noise Ratio) for each pulse is improved.
• Time Constant Selection: You can choose (\tau_d) (CR) and (\tau_i) (RC) to optimize for different detectors and pulse widths.
• Pulse Pile‐Up Management: A shaped pulse that returns to baseline faster can help mitigate overlapping events.
• Ease of Peak Detection: The shaped waveform has a well‐defined peak for amplitude measurement.

In radiation detection and nuclear spectroscopy, CR–RC² shaping is a classic approach to achieve near‐Gaussian pulses, giving excellent energy resolution with minimal ballistic deficit.

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6. Practical Tips

• Set the High‐Pass Cutoff below your pulse’s main frequency content but high enough to remove baseline drift.
• Set the Low‐Pass (RC²) Cutoff to shape the pulses for the desired rise and fall times. If too slow, pulses overlap more easily; if too fast, noise can dominate.
• Use an Appropriate Digital Gain to ensure that the shaped amplitude fits within the FPGA’s numeric range.
• Observe the Oscilloscope to verify that pulses have minimal overshoot and settle back to baseline before the next pulse arrives.

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7. Conclusion

A CR–RC² shaping amplifier combines a high‐pass differentiator (CR) with double low‐pass integrators (RC²). This classic design:

1. Removes baseline drift.
2. Attenuates high‐frequency noise.
3. Shapes pulses into a more uniform, easily measured form.

In Sci‐Compiler, these filters are realized via Butterworth IIR blocks (configured as high‐pass or low‐pass) plus an optional Gain stage. By choosing appropriate cutoff frequencies, you can replicate standard analog shaping times in a fully digital pipeline—a powerful technique for modern data acquisition systems in nuclear, medical, and industrial measurements.